product brief SPI-4 phase 1 core w/ fifos v1.0 for altera plds june 2001 odel ? are standards to silicon ? features ? oif-compliant SPI-4 phase 1 (compatible with amcc flexbus-4) with fifos ? atm, pac k e t over sonet (pos), and direct data mapping 1 modes ? single- and multi-link operation, scalable from 1 to 16 links. ? programmable per-port bandwidth allocation ? programmable fifo size with programmable almost empty/almost full thres holds . ? programmable burst size ? a u t o mat i c link select ion in t he source block based on source fifo threshold and flow control information. ? 64-bit data bus width. ? parity generation/checking over data and control words ? altera?s atlantic interface on user?s side. ? full synchronous design, exceeds: clk = 200 mhz ? fully automatic test bench including driver/monitor. ? easy to use in mux/demux and bridge functions standards compliance ? oif SPI-4 phase 1 ? amcc flexbus-4 1 direct data mapping is a raw data mode supported in amcc?s ganges device. benefits ? faster fpga and asic development for improved time-to-market with flexbus- 4 functions ? lower development cost through design reuse ? available source code licensing for easy design integration and migration to gate array s or asics ? ample design flexibility using control signals and generics/parameters ? verified functionality and standards compliance description the optical interworking forum?s (oif) spi- 4 phase 1 interface allows the interconnection of physic al layer devices to link layer devices in 10gb/s atm, pos, and ethernet applications. modelware?s SPI-4 phase 1 core performs the interface functions on both sides of the interface as shown in figure 1and figure 2. sp i 4 link layer co nt rol s t a t u s sp i - 4 i/ f p l ur ib us in t e r f a c e tx fi fo( s ) rx fifo ( s ) ph y lay er p r ocessor line t x dat a li ne r x dat a sp i 4 t x sp i 4 r x figure 1: SPI-4 phase 1 phy lay e r a pplication
SPI-4 phase 1 core v1.0 product brief june 2001 figure 2: SPI-4 phase 1 link lay e r a pplication on the system side, the SPI-4 phase 1 core interfaces to a single or to multiple links or ports via altera?s atlantic interface. the spi4tx block monitors the source fifos fill level and the flow control information received from the opposite side of the SPI-4 interface. if a source fifo has data and the flow control information for the corresponding channel indicates that it is ready to accept data, the spi4tx block initiates a data transfer from the source fifo towards the SPI-4 interfac e. the spi4rx block transmits the sink fifo status information to the opposite side according to the sink fifo almost-full flags. the spi4rx block stores data received for a particular link in that link?s fifo. sink fifo flags indicate to the user the presence of data in the fifo(s). ga te count the SPI-4 phase 1 core configured for 4 channels and targeted to apex ii uses: logic elements (les): 2700 embedded system blocks (esbs): 23 the above numbers include the core and a small amount of circuitry to implement a loopback on the atlantic interface. ph y layer link la y e r pro c essor spi4 c o n t r o l s ta tu s spi -4 i/f at l ant i c in te r f a c e spi4 r x spi4 t x sink fifo( s ) sourc e fifo( s ) li ne rx dat a li ne t x dat a design p a c k a ge the SPI-4 phase 1 core source code package contains: ? source code or netlist ? test bench (source code option) ? scripts and data files for simulation (behavioral, gate-level, and back- annotated), synthesis, and fpga layout ? detailed documentation: ? reference guide: core features, architecture, interfaces, and operation ? user's guide: core simulation, synthesis, and fpga layout step-by step procedures. suppor ted t ools ? mti modelsim for simulation ? exemplar leonardo spectrum for synthesis ? altera quartus or dering inf o r m a t ion modelware, inc. tel: (732)936-1808 fax: (732)936-1838 e-mail: sales@modelware.com internet: www.modelware.com t r ademar ks modelware is a registered trademark of modelware, inc. altera, quartus, and atlantic are trademarks of altera corporation. flexbus is a trademark of amcc.
product brief SPI-4 phase 1 core w/ fifos v1.0 for altera plds june 2001 odel are standards to silicon ? exemplar and leonardo spectrum are trademarks of exemplar logic, inc.
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